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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs general description the MAX11102/max11103/max11105/max11106/max11110 max11111/max11115/max11116/max11117 are 12-/10- /8-bit, compact, high-speed, low-power, successive approximation analog-to-digital converters (adcs). these high-performance adcs include a high-dynamic range sample-and-hold and a high-speed serial inter - face. these adcs accept a full-scale input from 0v to the power supply or to the reference voltage. the MAX11102/max11103/max11106/max11111 fea - ture dual, single-ended analog inputs connected to the adc core using a 2:1 mux. the devices also include a separate supply input for data interface and a dedicated input for reference voltage. in contrast, the single-chan - nel devices generate the reference voltage internally from the power supply. these adcs operate from a 2.2v to 3.6v supply and consume only 8.3mw at 3msps and 6.2mw at 2msps. the devices include full power-down mode and fast wake-up for optimal power management and a high- speed 3-wire serial interface. the 3-wire serial interface directly connects to spi k , qspi k , and microwire k devices without external logic. excellent dynamic performance, low voltage, low power, ease of use, and small package size make these con - verters ideal for portable battery-powered data-acquisi - tion applications, and for other applications that demand low-power consumption and minimal space. these adcs are available in a 10-pin tdfn package, 10-pin f max ? package, and a 6-pin sot23 package. these devices operate over the -40 n c to +125 n c tem - perature range. features s 2msps/3msps conversion rate, no pipeline delay s 12-/10-/8-bit resolution s 1-/2-channel, single-ended analog inputs s low-noise 73db snr s variable i/o: 1.5v to 3.6v (dual-channel only) allows the serial interface to connect directly to 1.5v, 1.8v, 2.5v, or 3v digital systems s 2.2v to 3.6v supply voltage s low power 8.3mw at 3msps 6.2mw at 2msps very low power consumption at 2.5a/ksps s external reference input (dual-channel devices only) s 1.3a power-down current s spi-/qspi-/microwire-compatible serial interface s 10-pin, 3mm x 3mm tdfn package s 10-pin, 3mm x 5mm max package s 6-pin, 2.8mm x 2.9mm sot23 package s wide -40 n c to +125 n c operation applications data acquisition portable data logging medical instrumentation battery-operated systems communication systems automotive systems 19-5245; rev 0; 4/10 note: all devices are specified over the -40c to +125c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ** future productcontact factory for availability. ordering information continued at end of data sheet. ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. max is a registered trademark of maxim integrated products, inc. part pin-package bits speed (msps) no. of channels MAX11102 aub+ 10 f max-ep* 12 2 2 MAX11102atb+** 10 tdfn-ep* 12 2 2 max11103 aub+ 10 f max-ep* 12 3 2 preliminary
2 ______________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ............................................................ -0.3v to +4v ref, ovdd, ain1, ain2, ain to gnd ........ -0.3v to the lower of (v dd + 0.3v) and +4v cs , sclk, chsel, dout to gnd ............ -0.3v to the lower of (v ovdd + 0.3v) and +4v agnd to gnd ...................................................... -0.3v to +0.3v input/output current (all pins) ........................................... 50ma continuous power dissipation (t a = +70 n c) 6-pin sot23 (derate 8.7mw/ n c above +70 n c) ......... ..696mw 10-pin tdfn (derate 24.4mw/ n c above +70 n c) ...... .1951mw 10-pin f max (derate 8.8mw/ n c above +70 n c) ...... ..707.3mw operating temperature range ....................... .-40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (MAX11102/max11103/max11105) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11103); f sclk = 32mhz, 50% duty cycle, 2msps (MAX11102/max11105), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) absolute maximum ratings parameter symbol conditions min typ max units dc accuracy resolution 12 bits 12 bits integral nonlinearity inl q 1 lsb differential nonlinearity dnl no missing codes q 1 lsb offset error oe q 0.3 q 3 lsb gain error ge excluding offset and reference errors q 1 q 3 lsb total unadjusted error tue q 1.5 lsb channel-to-channel offset matching MAX11102/max11103 q 0.4 lsb channel-to-channel gain matching MAX11102/max11103 q 0.05 lsb dynamic performance (MAX11102/max11105: f in = 0.5mhz, max11103: f in = 1mhz) signal-to-noise and distortion sinad max11103 70 72 db MAX11102/max11105 70 72.5 signal-to-noise ratio snr max11103 70.5 72 db MAX11102/max11105 70.5 73 total harmonic distortion thd max11103 -85 -75 db MAX11102/max11105 -85 -76 spurious-free dynamic range sfdr max11103 76 85 db MAX11102/max11105 77 85 intermodulation distortion imd f 1 = 1.0003mhz, f 2 = 0.99955mhz (max11103), f 1 = 500.15khz, f 2 = 499.56 khz (MAX11102/max11105) -84 db full-power bandwidth -3db point 40 mhz full-linear bandwidth sinad > 68db 2.5 mhz preliminary
_______________________________________________________________________________________ 3 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (MAX11102/max11103/max11105) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11103); f sclk = 32mhz, 50% duty cycle, 2msps (MAX11102/max11105), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units small-signal bandwidth 45 mhz crosstalk MAX11102/max11103 -90 db conversion rate throughput max11103 0.03 3 msps MAX11102/max11105 0.02 2 conversion time max11103 260 ns MAX11102/max11105 391 acquisition time t acq 52 ns aperture delay from cs falling edge 4 aperture jitter 15 ps serial-clock frequency f clk max11103 0.48 48 mhz MAX11102/max11105 0.32 32 analog input (ain1, ain2/ain) input voltage range v ina__ 0 v ref v input leakage current i ila 2na q 1 f a input capacitance c ain_ track 20 pf hold 4 external reference input (ref) (MAX11102/max11103) reference input voltage range v ref 1 v dd + 0.05 v reference input leakage current i ilr conversion stopped 0.005 q 1 f a reference input capacitance c ref 5 pf digital inputs (sclk, cs , chsel) digital input high voltage v ih (note 2) 75 %ovdd digital input low voltage v il (note 2) 25 %ovdd digital input hysteresis v hyst (note 2) 15 %ovdd digital input leakage current i il inputs at gnd or v dd 1na q 1 f a digital input capacitance c in 2 pf digital output (dout) output high voltage v oh i source = 200 f a (note 2) 85 %ovdd output low voltage v ol i sink = 200 f a (note 2) 15 %ovdd high-impedance leakage current i ol q 1.0 f a high-impedance output capacitance c out 4 pf power supply positive supply voltage v dd 2.2 3.6 v digital i/o supply voltage v ovdd MAX11102/max11103 1.5 v dd v preliminary
4 ______________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (MAX11102/max11103/max11105) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11103); f sclk = 32mhz, 50% duty cycle, 2msps (MAX11102/max11105), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) electrical characteristics (max11106/max11110/max11117)) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11106/max11117); f sclk = 32mhz, 50% duty cycle, 2msps (max11110), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units positive supply current (full-power mode) i vdd f sample = 3msps, max11103, v in = gnd 3.3 ma f sample = 2msps, MAX11102/max11105, v in = gnd 2.6 i ovdd max11103, v in = gnd 0.33 MAX11102, v in = gnd 0.22 positive supply current (full- power mode), no clock i vdd max11103 1.98 ma MAX11102/max11105 1.48 power-down current i pd leakage only 1.3 10 f a line rejection v dd = 2.2v to 3.6v, v ref = 2.2v 0.7 lsb/v timing characteristics (note 3) quiet time t q 4 ns cs pulse width t 1 10 ns cs fall to sclk setup t 2 5 ns cs falling until dout high impedance disabled t 3 (note 1) 1 ns data access time after sclk falling edge t 4 figure 2, v ovdd = 2.2v - 3.6v 15 ns figure 2, v ovdd = 1.5v - 2.2v 16.5 sclk pulse width low t 5 percentage of clock period 40 60 % sclk pulse width high t 6 percentage of clock period 40 60 % data hold time from sclk falling edge t 7 figure 3 5 ns sclk falling until dout high impedance t 8 figure 4 (note 1) 2.5 14 ns power-up time conversion cycle 1 cycle parameter symbol conditions min typ max units dc accuracy resolution 10 bits 10 bits integral nonlinearity inl q 0.5 lsb differential nonlinearity dnl no missing codes q 0.5 lsb offset error oe max11106/max11110 q 0.3 q 1.2 lsb max11117 q 0.5 q 1.65 gain error ge excluding offset and reference errors, max11106/max11110 q 0.15 q 1 lsb max11117 q 0.7 q 1.4 preliminary
_______________________________________________________________________________________ 5 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (max11106/max11110/max11117) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11106/max11117); f sclk = 32mhz, 50% duty cycle, 2msps (max11110), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units total unadjusted error tue q 1 lsb channel-to-channel offset matching max11106 q 0.1 lsb channel-to-channel gain matching max11106 q 0.1 lsb dynamic performance (max11106/max11117: f in = 1mhz, max11110: f in = 0.5mhz) signal-to-noise and distortion sinad max11106/max11117 59 61.5 db max11110 60.5 61.5 signal-to-noise ratio snr max11106/max11117 59 61.5 db max11110 60.5 61.5 total harmonic distortion thd max11106/max11117 -85 -74 db max11110 -85 -73 spurious-free dynamic range sfdr max11106/max11117 75 db max11110 75 intermodulation distortion imd f 1 = 1.0003mhz, f 2 = 0.99955mhz (max11106/maxx11117); f 1 = 500.15khz, f 2 = 499.56 khz (max11110) -82 db full-power bandwidth -3db point 40 mhz full-linear bandwidth sinad > 60db 2.5 mhz small-signal bandwidth 45 mhz crosstalk max11106 -90 db conversion rate throughput max11106/max11117 0.03 3 msps max11110 0.02 2 msps conversion time max11106/max11117 260 ns max11110 391 ns acquisition time t acq 52 ns aperture delay from cs falling edge 4 ns aperture jitter 15 ps serial-clock frequency f clk max11106/max11117 0.48 48 mhz max11110 0.32 32 analog input (ain1/ain2 for max11106) (ain for max11110/max11117) input voltage range v ina__ 0 v ref v input leakage current i ila 2na q 1 f a input capacitance c ain_ track 20 pf hold 4 external reference input (ref) (max11106) reference input voltage range v ref 1 v dd + 0.05 v reference input leakage current i ilr conversion stopped 0.005 q 1 f a preliminary
6 ______________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (max11106/max11110/max11117) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11106/max11117); f sclk = 32mhz, 50% duty cycle, 2msps (max11110), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units reference input capacitance c ref 5 pf digital inputs (sclk, cs , chsel) digital input high voltage v ih (note 2) 75 %ovdd digital input low voltage v il (note 2) 25 %ovdd digital input hysteresis v hyst (note 2) 15 %ovdd digital input leakage current i il inputs at gnd or v dd 0.001 q 1 f a digital input capacitance c in 2 pf digital output (dout) output high voltage v oh i source = 200a (note 2) 85 %ovdd output low voltage v ol i sink = 200a (note 2) 15 %ovdd high-impedance leakage current i ol q 1.0 f a high-impedance output capacitance c out 4 pf power supply positive supply voltage v dd 2.2 3.6 v digital i/o supply voltage v ovdd max11106 1.5 v dd v positive supply current (full- power mode) i vdd f sample = 3msps, max11106, v in = gnd 3.3 ma f sample = 2msps, max11110, v in = gnd 2.6 f sample = 3msps, max11117, v in = gnd 3.55 i ovdd max11106 0.33 positive supply current (full- power mode), no clock i vdd max11106/max11117 1.98 ma max11110 1.48 power-down current i pd leakage only 1.3 10 f a line rejection v dd = 2.2v to 3.6v, v ref = 2.2v 0.17 lsb/v timing characteristics (note 3) quiet time t q 4 ns cs pulse width t 1 10 ns cs fall to sclk setup t 2 5 ns cs falling until dout high impedance disabled t 3 (note 1) 1 ns data access time after sclk falling edge t 4 figure 2 v ovdd = 2.2v - 3.6v 15 ns v ovdd = 1.5v - 2.2v 16.5 sclk pulse width low t 5 percentage of clock period 40 60 % sclk pulse width high t 6 percentage of clock period 40 60 % data hold time from sclk falling edge t 7 figure 3 5 ns sclk falling until dout high impedance t 8 figure 4 (note 1) 2.5 14 ns power-up time conversion cycle 1 cycle preliminary
_______________________________________________________________________________________ 7 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (max11111/max11115/max11116) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11111/max11116); f sclk = 32mhz, 50% duty cycle, 2msps (max11115), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units dc accuracy resolution 8 bits 8 bits integral nonlinearity inl q 0.25 lsb differential nonlinearity dnl no missing codes q 0.25 lsb offset error oe q 0.45 q 0.75 lsb gain error ge excluding offset and reference errors q 0.04 q 0.5 lsb total unadjusted error tue q 0.75 lsb channel-to-channel offset matching max11111 0.025 lsb channel-to-channel gain matching max11111 0.025 lsb dynamic performance (max11111/max11116: f in = 1mhz, max11115: f in = 500khz) signal-to-noise and distortion sinad max11111/max11116 49 49.5 db max11115 49 49.5 signal-to-noise ratio snr max11111/max11116 49 49.5 db max11115 49 49.5 total harmonic distortion thd max11111/max11116 -70 -66 db max11115 -75 -67 spurious-free dynamic range sfdr max11111/max11116 63 66 db max11115 63 66 intermodulation distortion imd f 1 = 1.0003mhz, f 2 = 0.99955mhz (max11111/max11116); f 1 = 500.15khz, f 2 = 499.56khz (max11115) -65 db full-power bandwidth -3db point 40 mhz full-linear bandwidth sinad > 49db 2.5 mhz small-signal bandwidth 45 mhz crosstalk max11111 -90 db conversion rate throughput max11111/max11116 0.03 3 msps max11115 0.02 2 conversion time max11111/max11116 260 ns max11115 391 acquisition time t acq 52 ns aperture delay from cs falling edge 4 ns aperture jitter 15 ps serial-clock frequency f clk max11111/max11116 0.48 48 mhz max11115 0.32 32 preliminary
8 ______________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (max11111/max11115/max11116) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11111/max11116); f sclk = 32mhz, 50% duty cycle, 2msps (max11115), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units analog input (ain1/ain2 for max11111)(ain for max11115/max11116) input voltage range v ina_ 0 v ref v input leakage current i ila 2na q 1 f a input capacitance c ain track 20 pf hold 4 external reference input (ref) reference input voltage range v ref 1 v dd + 0.05 v reference input leakage current i ilr conversion stopped 0.005 q 1 f a reference input capacitance c ref 5 pf digital inputs (sclk, cs ) digital input high voltage v ih (note 2) 75 %ovdd digital input low voltage v il (note 2) 25 %ovdd digital input hysteresis v hyst (note 2) 15 %ovdd digital input leakage current i il inputs at gnd or v dd 0.001 q 1 f a digital input capacitance c in 2 pf digital output (dout) output high voltage v oh i source = 200a (note 2) 85 %ovdd output low voltage v ol i sink = 200a (note 2) 15 %ovdd high-impedance leakage current i ol q 1.0 f a high-impedance output capacitance c out 4 pf power supply positive supply voltage v dd 2.2 3.6 v digital i/o supply voltage v ovdd max11111 1.5 v dd v positive supply current (full- power mode) i vdd f sample = 3msps, max11111, v in = gnd 3.3 ma f sample = 2msps, max11115, v in = gnd 2.6 f sample = 3msps, max11116, v in = gnd 3.55 positive supply current (full- power mode), no clock i vdd max11111/max11116, v in = gnd 1.98 ma max11115, v in = gnd 1.48 power-down current i pd leakage only 1.3 10 f a line rejection v dd = 2.2v to 3.6v, v ref = 2.2v 0.17 lsb/v timing characteristics (note 3) quiet time t q 4 ns cs pulse width t 1 10 ns cs fall to sclk setup t 2 5 ns preliminary
_______________________________________________________________________________________ 9 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs electrical characteristics (max11111/max11115/max11116) (continued) (v dd = 2.2v to 3.6v, v ref = v dd , v ovdd = v dd , f sclk = 48mhz, 50% duty cycle, 3msps (max11111/max11116); f sclk = 32mhz, 50% duty cycle, 2msps (max11115), c dout = 10pf, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) note 1: guaranteed by design and characterization; not production tested. note 2: v ovdd is tied to v dd internally for all sot devices. note 3: all timing specifications given are with a 10pf load capacitor. parameter symbol conditions min typ max units cs falling until dout high impedance disabled t 3 (note 1) 1 ns data access time after sclk falling edge t 4 figure 2 v ovdd = 2.2v - 3.6v 15 ns v ovdd = 1.5v - 2.2v 16.5 sclk pulse width low t 5 percentage of clock period 40 60 % sclk pulse width high t 6 percentage of clock period 40 60 % data hold time from sclk falling edge t 7 figure 3 5 ns sclk falling until dout high impedance t 8 figure 4 (note 1) 2.5 14 ns power-up time conversion cycle 1 cycles preliminary
10 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs figure 1. interface signals for maximum throughput, 12-bit devices figure 2. setup time after sclk falling edge figure 3. hold time after sclk falling edge figure 4. sclk falling edge dout three-state 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 1 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout sclk high impedance t 6 t 2 t 5 t 1 0 sample sample 0 0 (msb) t 3 t 4 t 7 t 8 t quiet t convert 1/f sample t acq cs high impedance v ih v il new data old data dout sclk t 4 v ih v il old data new data dout sclk t 7 high impedance dout sclk t 8 preliminary
______________________________________________________________________________________ 11 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs max typical operating characteristics (max11103aub+, t a = +25c, unless otherwise noted.) thd vs. analog input frequency MAX11102 toc07 f in (khz) thd (db) -110 -100 -90 -80 -70 -60 -120 1200 900 600 300 0 1500 f s = 3msps snr and sinad vs. analog input frequency MAX11102 toc06 f in (khz) sinad snr snr and sinad (db) 1200 900 600 300 71 72 73 74 75 70 0 1500 f s = 3msps histogram for 30,000 conversions MAX11102 toc05 digital code output code count 2049 2048 2047 5000 10,000 15,000 20,000 25,000 30,000 35,000 0 2046 2050 gain error vs. temperature MAX11102 toc04 temperature (?c) gain error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2 -1 0 1 2 3 -3 -40 125 offset error vs. temperature MAX11102 toc03 temperature (?c) offset error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2 -1 0 1 2 3 -3 -40 125 differential nonlinearity vs. digital output code MAX11102 toc02 digital output code dnl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3.0msps integral nonlinearity vs. digital output code MAX11102 toc01 digital output code inl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3.0msps preliminary
12 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs max typical operating characteristics (continued) (max11103aub+, t a = +25c, unless otherwise noted.) snr vs. reference voltage MAX11102 toc13 v ref (v) snr (db) 3.4 3.2 3.0 2.8 2.6 2.4 71.5 72.0 72.5 73.0 73.5 71.0 2.2 3.6 f s = 3msps f in = 1.0183mhz analog supply current vs. temperature MAX11102 toc12 temperature (?c) i vdd (ma) 110 95 80 65 50 35 20 5 -10 -25 2.3 2.6 2.9 3.2 3.5 2.0 -40 125 v dd = 2.2v v dd = 3.6v v dd = 3.0v reference current vs. sampling rate MAX11102 toc11 f s (ksps) i ref (a) 2500 2000 1500 1000 500 50 100 150 200 0 0 3000 1mhz sine-wave input (16,834-point fft plot) MAX11102 toc10 frequency (khz) a hd3 = -91.2db amplitude (db) -100 -80 -60 -40 -20 0 -120 1000 1250 750 500 250 0 1500 f s = 3.0msps f in = 1.0183mhz a hd2 = -110.3db thd vs. input resistance MAX11102 toc09 r in (i) thd (db) -95 -90 -85 -80 -75 -70 -100 80 60 40 20 0 100 f s = 3.0msps f in = 1.0183mhz sfdr vs. analog input frequency MAX11102 toc08 f in (khz) sfdr (db) 80 90 100 110 120 130 70 1200 900 600 300 0 1500 f s = 3msps preliminary
______________________________________________________________________________________ 13 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs sot typical operating characteristics (max11105aub+, t a = +25c, unless otherwise noted.) snr and sinad vs. analog input frequency MAX11102 toc19 f in (khz) snr sinad snr and sinad (db) 800 600 400 200 72.0 72.5 73.0 73.5 71.5 0 1000 f s = 2.0msps histogram for 30,000 conversions MAX11102 toc18 digital code output code count 2049 2048 2047 5000 10,000 15,000 20,000 25,000 30,000 35,000 0 2046 2050 gain error vs. temperature MAX11102 toc17 temperature (?c) gain error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -3 -2 -1 0 1 2 -4 -40 125 offset error vs. temperature MAX11102 toc16 temperature (?c) offset error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2 -1 0 1 2 3 -3 -40 125 differential nonlinearity vs. digital output code MAX11102 toc15 digital output code dnl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 2.0msps integral nonlinearity vs. digital output code MAX11102 toc14 digital output code inl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 2.0msps preliminary
14 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs sot typical operating characteristics (continued) (max11105aub+, t a = +25c, unless otherwise noted.) snr vs. reference voltage (v dd ) MAX11102 toc25 v dd (v) snr (db) 3.4 3.2 3.0 2.8 2.6 2.4 72 73 74 75 71 2.2 3.6 f s = 2.0msps f in = 500.122khz analog supply current vs. temperature MAX11102 toc24 temperature (?c) i vdd (ma) 110 95 80 65 50 35 20 5 -10 -25 1.8 2.0 2.2 2.4 2.6 1.6 -40 125 v dd = 2.2v v dd = 3.6v v dd = 3.0v 500khz sine-wave input (16,834-point fft plot) MAX11102 toc23 frequency (khz) a hd3 = -96.5db amplitude (db) -100 -80 -60 -40 -20 0 -120 750 500 250 0 1000 f s = 2.0msps f in = 500.122khz a hd2 = -92.0db thd vs. input resistance MAX11102 toc22 r in (i) thd (db) -95 -90 -85 -80 -75 -100 80 60 40 20 0 100 f s = 2.0msps f in = 500.122khz sfdr vs. analog input frequency MAX11102 toc21 f in (khz) sfdr (db) 85 90 95 100 105 110 80 800 600 400 200 0 1000 f s = 2.0msps thd vs. analog input frequency MAX11102 toc20 f in (khz) thd (db) -105 -100 -95 -90 -85 -80 -110 800 600 400 200 0 1000 f s = 2.0msps preliminary
______________________________________________________________________________________ 15 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs pin description pin configurations 1 3 4 10 8 7 sclk ovdd chsel *connect exposed pad to ground plane. devices do not operate when ep is not connected to ground! agnd ref MAX11102 max11103 max11106 max11111 2 9 dout ain2 ain1 5 6 cs v dd tdfn top view ep* ep* + top view + top view gnd sclk ain 1 6 cs 5 dout v dd max11105 max11110 max11115 max11116 max11117 sot23 2 3 4 + max 2 9 dout ain2 1 10 sclk ain1 ovdd agnd 3 8 chsel ref 7 cs v dd 6 MAX11102 max11103 4 5 pin name function tdfn max sot23 1 1 ain1 analog input channel 1. single-ended analog input with respect to agnd with range of 0v to v ref . 2 2 ain2 analog input channel 2. single-ended analog input with respect to agnd with range of 0v to v ref. 3 ain analog input channel. single-ended analog input with respect to gnd with range of 0v to v dd. 2 gnd ground. connect gnd to the gnd ground plane. 3 3 agnd analog ground. connect agnd directly the gnd ground plane. 4 4 ref external reference input. ref defines the signal range of the input signal ain1/ain2: 0v to v ref . the range of v ref is 1v to v dd. bypass ref to agnd with 10 f f || 0.1 f f capacitor. 5 5 1 v dd positive supply voltage. bypass v dd with a 10 f f || 0.1 f f capacitor to gnd. v dd range is 2.2v to 3.6v. for the sot23 package, v dd also defines the signal range of the input signal ain: 0v to v dd . 6 6 6 cs active-low chip-select input. the falling edge of cs samples the analog input signal, starts a conversion, and frames the serial data transfer. 7 7 chsel channel select. set chsel high to select ain2 for conversion. set chsel low to select ain1 for conversion. 8 8 ovdd digital interface supply for sclk, cs , dout, and chsel. the ovdd range is 1.5v to v dd . bypass ovdd with a 10 f f || 0.1 f f capacitor to gnd. 9 9 5 dout three-state serial data output. adc conversion results are clocked out on the falling edge of sclk, msb first. see figure 1. 10 10 4 sclk serial clock input. sclk drives the conversion process. dout is updated on the fall - ing edge of sclk. see figures 2 and 3. ep ep gnd exposed pad. connect ep directly to a solid ground plane. devices do not operate when ep is not connected to ground! preliminary
16 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs functional diagrams typical operating circuit cdac mux ref ain2 ain1 chsel control logic sar output buffer sclk cs v dd ovdd dout MAX11102/max11103/ max11106/max11111 cdac ain control logic sar output buffer sclk cs dout v dd gnd (ep) v ref = v dd max11105/max11110/ max11115/max11116/ max11117 gnd (ep) agnd MAX11102 max11103 max11106 max11111 v dd ovdd sclk cpu dout cs chsel ain1 sck miso ain2 agnd ref +3v v ovdd analog inputs +2.5v ss max11105 max11110 max11115 max11116 max11117 v dd cpu ain gnd (ep) +3v analog input dout miso sclk sck cs ss gnd (ep) preliminary
______________________________________________________________________________________ 17 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs detailed description the MAX11102/max11103/max11105/max11106/max11110/ max11111/max11115/max11116/max11117 are fast, 12-/10-/8-bit, low-power, single-supply adcs. the devices operate from a 2.2v to 3.6v supply and con - sume only 8.3mw at 3msps and 6.2mw at 2msps. the 3msps devices are capable of sampling at full rate when driven by a 48mhz clock and the 2msps devices can sample at full rate when driven by a 32mhz clock. the dual-channel devices provide a separate digital supply input (ovdd) to power the digital interface enabling communication with 1.5v, 1.8v, 2.5v, or 3v digital systems. the conversion result appears at dout, msb first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. a 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. see figures 1 and 5. the dual-channel devices feature a dedicated refer - ence input (ref). the input signal range for ain1/ain2 is defined as 0v to v ref with respect to agnd. the single-channel devices use v dd as the reference. the input signal range of ain is defined as 0v to v dd with respect to gnd. these adcs include a power-down feature allowing minimized power consumption at 2.5 f a/ksps for lower throughput rates. the wake-up and power-down feature is controlled using the spi interface as described in the operating modes section. serial interface the devices feature a 3-wire serial interface that directly connects to spi, qspi, and microwire devices without external logic. figures 1 and 5 show the interface sig - nals for a single conversion frame to achieve maximum throughput. the falling edge of cs defines the sampling instant. once cs transitions low, the external clock signal (sclk) controls the conversion. the sar core successively extracts binary-weighted bits in every clock cycle. the msb appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. all extracted data bits appear suc - cessively on the data bus with the lsb appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. the serial data stream of conversion bits is preceded by a leading zero and succeeded by trailing zeros. the data output (dout) goes into high-impedance state dur - ing the 16th clock cycle. figure 5. 10-/8-bit timing diagrams sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 1 sample sample cs dout high impedance high impedance high impedance high impedance 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 sample sample sclk cs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 1 dout 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 preliminary
18 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs to sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. for lower sample rates, the cs falling edge can be delayed leaving dout in a high-impedance condition. pull cs high after the 10th sclk falling edge (see the operating modes section). analog input the devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0 to v ref for the dual-channel devices and 0 to v dd for the single-channel devices. figure 6 shows an equivalent circuit for the analog input ain (for single-channel devices) and ain1/ain2 (for dual-channel devices). internal protection diodes d1/d2 confine the analog input voltage within the power rails (v dd , gnd). the analog input voltage can swing from gnd - 0.3v to v dd + 0.3v without damaging the device. the electric load presented to the external stage driv - ing the analog input varies depending on which mode the adc is in: track mode vs. conversion mode. in track mode, the internal sampling capacitor c s (16pf) has to be charged through the resistor r (r = 50 i ) to the input voltage. for faithful sampling of the input, the capacitor voltage on c s has to settle to the required accuracy dur - ing the track time. the source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. the thd vs. input resistance graph in the typical operating characteristics shows thd sensitivity as a function of the signal source imped - ance. keep the source impedance at a minimum for high-dynamic performance applications. use a high- performance op amp such as the max4430 to drive the analog input, thereby decoupling the signal source and the adc. while the adc is in conversion mode, the sampling switch is open presenting a pin capacitance, c p (c p = 5pf), to the driving stage. see the applications information section for information on choosing an appropriate buffer for the adc. operating modes the ics offer two modes of operation: normal mode and power-down mode. the logic state of the cs signal during a conversion activates these modes. the power- down mode can be used to optimize power dissipation with respect to sample rate. normal mode in normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. figure 7 shows the timing diagram of these devices in normal mode. the falling edge of cs samples the analog input signal, starts a conversion, and frames the serial data transfer. to remain in normal mode, keep cs low until the falling edge of the 10th sclk cycle. pulling cs high after the 10th sclk falling edge keeps the part in normal mode. however, pulling cs high before the 10th sclk falling edge terminates the conversion, dout goes into high- impedance mode, and the device enters power-down mode. see figure 8. figure 6. analog input circuit figure 7. normal mode c p ain1/ain2 v dd ain d2 d1 r c s switch closed in track mode switch open in conversion mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 sclk pull cs high after the 10th sclk falling edge keep cs low until after the 10th sclk falling edge cs dout valid data high impedance high impedance preliminary
______________________________________________________________________________________ 19 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs power-down mode in power-down mode, all bias circuitry is shut down drawing typically only 1.3 f a of leakage current. to save power, put the device in power-down mode between conversions. using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. entering power-down mode to enter power-down mode, drive cs high between the 2nd and 10th falling edges of sclk (see figure 8). by pulling cs high, the current conversion terminates and dout enters high impedance. exiting power-down mode to exit power-down mode, implement one dummy con - version by driving cs low for at least 10 clock cycles (see figure 9). the data on dout is invalid during this dummy conversion. the first conversion following the dummy cycle contains a valid conversion result. the power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. the power-up time for 3msps operation (48mhz sclk) is 333ns. the power-up time for 2msps operation (32mhz sclk) is 500ns. adc transfer function the output format is straight binary. the code transi - tions midway between successive integer lsb values such as 0.5 lsb, 1.5 lsb, etc. the lsb size for single- channel devices is v dd /2 n and for dual-channel devices is v ref /2 n , where n is the resolution. the ideal transfer characteristic is shown in figure 10. figure 8. entering power-down mode figure 9. exiting power-down mode figure 10. adc transfer function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 high impedance invalid data sclk cs dout invalid data or high impedance high impedance pull cs high after the 2nd and before the 10th sclk falling edge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 high impedance high impedance high impedance sclk cs dout invalid data (dummy conversion) valid data fs - 1.5 x lsb output code analog input (lsb) 111...111 111...110 111...101 0 1 2 3 2 n -2 2 n -1 2 n 000...000 000...001 000...010 full scale (fs): ain1/ain2 = ref (tdfn, max) ain = v dd (sot) n = resolution preliminary
20 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs supply current vs. sampling rate for applications requiring lower throughput rates, the user can reduce the clock frequency (f sclk ) to lower the sample rate. figure 11 shows the typical supply current (i vdd ) as a function of sample rate (f s) for the 3msps devices. the part operates in normal mode and is never powered down. figure 13 pertains to the 2msps devices. the user can also power down the adc between conver - sions by using the power-down mode. figure 12 shows for the 3msps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (i vdd ) drops accordingly over time. figure 14 pertains to the 2msps devices. figure 11. supply current vs. sample rate (normal operating mode, 3msps devices) figure 13. supply current vs. sample rate (normal operating mode, 2msps devices) figure 12. supply current vs. sample rate (device powered down between conversions, 3msps devices) figure 14. supply current vs. sample rate (device powered down between conversions, 2msps devices) MAX11102 fig11 f s (ksps) i vdd (ma) 2500 2000 1500 1000 500 1 2 3 4 5 0 0 3000 v dd = 3v f sclk = variable 16 cycles/conversion f s (ksps) i vdd (ma) 800 600 400 200 0.5 1.0 1.5 2.0 2.5 3.0 0 0 1000 v dd = 3v f sclk = 48mhz 1500 1000 500 1 2 3 4 0 0 2000 v dd = 3v f sclk = variable 16 cycles/conversion f s (ksps) i vdd (ma) f s (ksps) i vdd (ma) 400 300 200 100 0.5 1.0 1.5 2.0 0 0 500 v dd = 3v f sclk = 32mhz preliminary
______________________________________________________________________________________ 21 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs figure 15. channel select timing diagram dual-channel operation the MAX11102/max11103/max11106/max11111 fea - ture dual-input channels. these devices use a channel- select (chsel) input to select between analog input ain1 (chsel = 0) or ain2 (chsel = 1). as shown in figure 15, the chsel signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. 14-cycle conversion mode the ics can operate with 14 cycles per conversion. figure 16 shows the corresponding timing diagram. observe that dout does not go into high-impedance mode. also, observe that t acq needs to be sufficiently long to guarantee proper settling of the analog input voltage. see the electrical characteristics table for t acq requirements and the analog input section for a descrip - tion of the analog inputs. applications information layout, grounding, and bypassing for best performance, use pcbs with a solid ground plane. ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the adc package. noise in the v dd power supply, ovdd, and ref affects the adcs perfor - mance. bypass the v dd , ovdd, and ref to ground with 0.1 f f and 10 f f bypass capacitors. minimize capacitor lead and trace lengths for best supply-noise rejection. choosing an input amplifier it is important to match the settling time of the input amplifier to the acquisition time of the adc. the conver - sion results are accurate when the adc samples the input signal for an interval longer than the input signals worst-case settling time. by definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches figure 16. 14-clock cycle operation 1 data channel ain2 data channel ain1 sclk chsel dout cs 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 dout sclk (msb) sample sample 1/f sample t acq t convert cs 2 3 4 d10 d11 5 6 7 8 9 10 11 12 13 14 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 preliminary
22 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs and stays within a given error band centered on the resulting steady-state amplifier output level. the adc input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. during this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. this error can be estimated by looking at the settling of an rc time constant using the input capacitance and the source impedance over the acquisition time period. figure 17 shows a typical application circuit. the max4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. see the thd vs. input resistance graph in the typical operating characteristics . choosing a reference for devices using an external reference, the choice of the reference determines the output accuracy of the adc. an ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage indepen - dent of changes in load current, temperature, and time. considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. figure 17 shows a typical application circuit using the max6126 to provide the reference voltage. the max6033 and max6043 are also excellent choices. figure 17. typical application circuit MAX11102 max11103 max11106 max11111 max6126 ovdd v ovdd 3v sclk cpu dout chsel sck miso cs ss 0.1f 1f 10f 0.1f agnd ain1 ain1 v dc 3 1 5 2 2 4 ain2 v dd 7 2 1 8 4 3 10f 0.1f 0.1f 0.1f +5v -5v 470pf cog capacitor 10i 500i 470pf cog capacitor 10f +3v 10f 0.1f 0.1f 10f ref outf in nr outs gnds gnd ep max4430 ain2 v dc 3 1 5 4 0.1f +5v -5v 10i 10f 0.1f 10f max4430 500i 500i 500i 100pf cog 100pf cog preliminary
______________________________________________________________________________________ 23 MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of 1 lsb or less guarantees no mis- sing codes and a monotonic transfer function. offset error the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, agnd + 0.5 lsb. gain error the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, v ref - 1.5 lsb. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. signal-to-noise ratio (snr) snr is a dynam ic figure of merit that indicates the con - verters noise performance. for a waveform perfectly reconstructed from digital samples, the theoretical maxi - mum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr (db) (max) = (6.02 x n + 1.76) (db) in reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade snr. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise ratio and distortion (sinad) sinad is a dynami c figure of merit that indicates the converters noise and distortion performance. sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distor - tion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset: . ( ) rms rms signal sinad(db) 20 log noise distortion ? ? = ? ? + ? ? ? ? total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: 2 2 2 2 2 3 4 5 1 v v v v thd 20 log v ? ? + + + ? ? = ? ? ? ? ? ? where v 1 is the fundamental amplitude and v 2 Cv 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is a dynam ic figure of merit that indicates the low - est usable input signal amplitude. sfdr is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spuri - ous component, excluding dc offset. sfdr is specified in decibels with respect to the carrier (dbc). full-power bandwidth full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3db for a full-scale input. full-linear bandwidth full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (sinad) is equal to a specified value. intermodulation distortion any device with nonlinearities creates distortion prod - ucts when two sine waves at two different frequencies (f 1 and f 2 ) are applied into the device. intermodulation distortion (imd) is the total power of the im2 to im5 inter - modulation products to the nyquist frequency relative to the total input power of the two input tones, f 1 and f 2 . the individual input tone levels are at -6dbfs . preliminary
24 _____________________________________________________________________________________ MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs note: all devices are specified over the -40c to +125c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ** future productcontact factory for availability. ordering information (continued) chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package bits speed (msps) no. of channels max11103atb+** 10 tdfn-ep* 12 3 2 max11105 aut+ 6 sot23 12 2 1 max11106 atb+** 10 tdfn-ep* 10 3 2 max11110 aut+ 6 sot23 10 2 1 max11111 atb+** 10 tdfn-ep* 8 3 2 max11115 aut+ 6 sot23 8 2 1 max11116 aut+ 6 sot23 8 3 1 max11117 aut+ 6 sot23 10 3 1 package type package code document no. 10 tdfn-ep t1033+2 21-0137 10 f max u10+2 21-0061 6 sot23 u6+1 21-0058 preliminary
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 25 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX11102/03/05/06/10/11/15/16/17 2msps/3msps, low-power, serial 12-/10-/8-bit adcs revision history revision number revision date description pages changed 0 4/10 initial release preliminary

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